#ChipScope Core Inserter Project File Version 3.0
#Fri Jan 22 00:02:27 EST 2010
Project.device.designInputFile=C\:\\Documents and Settings\\sxs5464\\Desktop\\RapidFPGA\\code\\Xilinx Projects\\ImagerController\\I2CmasterDemo_cs.ngc
Project.device.designOutputFile=C\:\\Documents and Settings\\sxs5464\\Desktop\\RapidFPGA\\code\\Xilinx Projects\\ImagerController\\I2CmasterDemo_cs.ngc
Project.device.deviceFamily=13
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\Documents and Settings\\sxs5464\\Desktop\\RapidFPGA\\code\\Xilinx Projects\\ImagerController\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=7
Project.filter<0>=*uut*
Project.filter<1>=uut
Project.filter<2>=
Project.filter<3>=*out*
Project.filter<4>=*send*
Project.filter<5>=*ssend*
Project.filter<6>=*i2c_clk*
Project.icon.boundaryScanChain=1
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=FPGA_Clk_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataDepth=8192
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=9
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=UUT/nstate_FFd1
Project.unit<0>.triggerChannel<0><1>=UUT/nstate_FFd4
Project.unit<0>.triggerChannel<0><2>=UUT/nstate_FFd5
Project.unit<0>.triggerChannel<0><3>=UUT/nstate_FFd6
Project.unit<0>.triggerChannel<0><4>=UUT/nstate_FFd7
Project.unit<0>.triggerChannel<0><5>=UUT/nstate_FFd8
Project.unit<0>.triggerChannel<0><6>=UUT/nstate_FFd9
Project.unit<0>.triggerChannel<1><0>=UUT/Mtridata_in_i2c
Project.unit<0>.triggerChannel<2><0>=CLK/sI2C_Clk
Project.unit<0>.triggerChannel<3><0>=SW_3_IBUF
Project.unit<0>.triggerChannel<4><0>=
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCount<1>=1
Project.unit<0>.triggerMatchCount<2>=1
Project.unit<0>.triggerMatchCount<3>=1
Project.unit<0>.triggerMatchCount<4>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchCountWidth<1><0>=0
Project.unit<0>.triggerMatchCountWidth<2><0>=0
Project.unit<0>.triggerMatchCountWidth<3><0>=0
Project.unit<0>.triggerMatchCountWidth<4><0>=0
Project.unit<0>.triggerMatchType<0><0>=0
Project.unit<0>.triggerMatchType<1><0>=0
Project.unit<0>.triggerMatchType<2><0>=0
Project.unit<0>.triggerMatchType<3><0>=0
Project.unit<0>.triggerMatchType<4><0>=0
Project.unit<0>.triggerPortCount=4
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortIsData<1>=true
Project.unit<0>.triggerPortIsData<2>=true
Project.unit<0>.triggerPortIsData<3>=true
Project.unit<0>.triggerPortIsData<4>=true
Project.unit<0>.triggerPortWidth<0>=7
Project.unit<0>.triggerPortWidth<1>=1
Project.unit<0>.triggerPortWidth<2>=1
Project.unit<0>.triggerPortWidth<3>=1
Project.unit<0>.triggerPortWidth<4>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
